As integrated circuit technologies continue to advance to nanometer technology node, there are continuing efforts to increase density and performance, and reduce costs. Manufacturers in the field have begun to consider the transition from three-dimensional planar complimentary metal-oxide-semiconductor (CMOS) transistor structures to fin field effect transistor (FinFET) structures. The FinFET is a new CMOS transistor, which can adjust threshold voltage (Vth) of the device, further reduce static power consumption. Compared with the planar transistor, the FinFET structures have improved control of the channel, thereby reducing short channel effect.
Currently, the FinFET structures may generally include three-terminal FinFET (3T-FinFET) structures and four-terminal FinFET (4T-FinFET) structures. Wherein, the 3T-FinFET structure includes three terminals, which is a source, a drain and a gate across the fin of the 3T-FinFET, the source and the drain locate at opposing ends of the fin. Since three sides of the fin are controlled by the gate, which would have a better control to carriers in active region and provide greater drive current than that of conventional MOS structures, thereby improving the device performance and the 3T-FinFET structure has been widely used. the 4T-FinFET (dual-gate FinFET) structure includes four terminals, a source, a drain and two separated gates on each side of the fin respectively, which is a drive gate and a control gate, the source and the drain locate at opposing ends of the fin. The channel current of the fin can be controlled by the two gates independently, and the threshold voltage of the drive gate can effectively be changed by adjusting size of the control gate, to improve device performance. Therefore, in practical applications, a low current leakage of core logic circuit would be requires for the dual-gate FinFET.
The difference of the 4T-FinFET and the 3T-FinFET is that, the 4T-FinFET has two independent gates. Therefore, in the production of the 4T-FinFET, there is a process in prior art to separate two gates of the 4T-FinFET. However, the height of the formed driving gate and the control gate after such process are the same, which make it difficult to further reduce the leakage current at the bottom of effective channel.